The present invention relates to a method of forming a semiconductor memory device, and more particularly to a method of forming a semiconductor memory device using a ferroelectric or high dielectric.
A ferroelectric memory serving as a capacitor has a combined structure of a semiconductor with a ferroelectric layer such as SrBi.sub.2 TaO.sub.9 (hereinafter referred to as SBT), wherein the capacitor is capable of storing "0" and "1" signals by utilizing residual polarization of the ferroelectric. FIG. 1 is a graph illustrative of variations in polarization of a ferroelectric over bias voltage applied to the ferroelectric.
After a positive bias has been applied to the ferroelectric capacitor, then the bias voltage becomes zero. Nevertheless, the polarization is not returned to zero, but a residual polarization Pr remains. By contrast, after a negative bias has been applied to the ferroelectric capacitor, then the bias voltage becomes zero. Nevertheless, the polarization is not returned to zero, but a residual polarization--Pr remains. It is possible to judge "0" and "1" by reading out the residual polarization. This means that the capacity of the ferroelectric is used as a memory. "1" or "0" remains stored after the power off, for which reason the ferroelectric memory is performed as anon-volatile memory.
Fabrication processes for that memory are disclosed in International Patent Publication No. WO93/12542. FIGS. 2A through 2P are fragmentary cross sectional elevation views illustrative of a conventional method of forming a semiconductor memory device using ferroelectric.
With reference to FIG. 2A, a bottom electrode layer 2 is formed on a silicon dioxide layer 1. The bottom electrode layer 2 comprises laminations of a Pt layer extending over the silicon dioxide layer 1 and a Ti layer extending over the Pt layer. A ferroelectric layer 3 is formed on the bottom electrode layer 2. The ferroelectric layer 3 is made of SBT. A top electrode layer 4 made of Pt is provided on the ferroelectric layer 3.
With reference to FIG. 2B, a photo-resist layer 5 is selectively provided on the top electrode layer 4.
With reference to FIG. 2C, the top electrode 4 partially covered by the photo-resist film 5 serving as a mask is etched by a sputter effect of Ar ions in an ion milling method.
With reference to FIGS. 2D and 2E, the ferroelectric layer 3 is subsequently etched by use of the photo-resist as a mask by the sputter effect of Ar ions in the ion milling method so as to define ridged laminations of the of the ferroelectric layer 3 and the top electrode 4 and also show partially the top surface of the bottom electrode 2.
With reference to FIG. 2F, the used photo-resist is removed by a plasma etching method such as ashing of oxygen plasma.
With reference to FIG. 2G, a heat treatment to the substrate 1 is carried out at a temperature of 800.degree. C. in oxygen atmosphere for 30 minutes to recover crystal defects having been generated in the ferroelectric layer 3 in the above etching processes. This heat treatment is necessary because if no heat treatment were carried out, then a density of leak current is not less than 1 A/cm.sup.2 when applied with a voltage of 3V whereby the capacitor is not longer useable. A temperature of 800.degree. C. corresponds to a temperature of crystallization of the ferroelectric layer 3, for which reason the above heat treatment can recover the crystal defects whereby the density of leak current is reduced to the order of 10.sup.-7 A/m.sup.2 when applied with a voltage of 5V. As a result, the capacitor is useable.
Further, the capacitor is processed to form a semiconductor memory device by forming interconnections.
With reference to FIG. 2H, as described above, the capacitor is fabricated which comprises the ferroelectric layer 3 sandwiched by the top and bottom electrode layers 4 and 2.
With reference to FIG. 2I, an inter-layer insulator 11 made of non-doped silicon glass is entirely formed which covers the capacitor and the silicon oxide film 1.
With reference to FIG. 2J, a photo-resist film 12 is selectively formed on the inter-layer insulator 11 so that an opening of the photo-resist film 12 is positioned over the top electrode 4.
With reference to FIG. 2K, the inter-layer insulator 11 except for it part covered by the photo-resist 12 is selectively etched by a plasma etching by use of CHF.sub.3 to form a contact hole in the inter-layer insulator 11 so that a part of the top surface of the top electrode 4 is shown through the contact hole. With reference to FIG. 2L, the used photo-resist 12 is removed.
With reference to FIG. 2K an interconnection layer 13 is entirely formed which extends over the inter-layer insulator 11 and within the contact hole so that the interconnection layer 13 is made into contact with the top surface of the top electrode 4. The interconnection layer 13 comprises laminations of a titanium layer, a titanium nitride layer laminated on the titanium layer and an aluminum layer laminated on the titanium nitride layer.
With reference to FIG. 2N, a photo-resist film 14 is selectively formed on the interconnection layer 13.
With reference to FIG. 2O, the interconnection layer 13 except for its part covered by the photo-resist film 14 is selectively etched by a plasma etching using BCl.sub.3.
With reference to FIG. 2P, the used photo-resist film 14 is removed whereby the semiconductor memory device is completed.
The conventional method described above has the following problems. The laminations of the bottom electrode layer 2, the ferroelectric layer 3 and the top electrode layer 4 have been formed before the laminations are patterned by the ion-milling method which is, however, disadvantageous in an extremely low etching rate of 12 nm/min. because of a physical etching by use of Ar ions. Usually, the ferroelectric layer 3 of SBT has a thickness of about 180 nanometers. It takes about 15 minutes to etch the ferroelectric layer 3 by the ion-milling method. This means that the productivity is extremely low when the ion-milling method is used to define the capacitor. In this ion-milling method, ion impacts by Ar sputter atoms of the ferroelectric layer, for which reason etching damage is relatively large and a large number of crystal defects are formed in the ferroelectric layer. This large number of the crystal defects causes an increased leakage of current flowing through the ferroelectric layer. To prevent the leakage of current, it is required to recover the crystal defects by carrying out a heat treatment at a high temperature of 800.degree. C. which is also required to crystallize SBT of the ferroelectric layer.
The above capacitor might be formed over a base layer or a base substrate having integrated circuits which include impurity doped layers and interconnections. The heat treatment at such a high temperature provides undesirable influences to distributions of impurity concentrations of the impurity doped layers and materials of the interconnections. In order to prevent the undesirable influences to the distributions of impurity concentrations of the impurity doped layers and the materials of the interconnections, it is required to do a possible reduction in the number of the high temperature heat treatments or to drop the temperature of the heat treatment down to, for example, 600.degree. C. which might provide no substantive influence to the base layer or the base substrate.
The etching damage is caused not only when the ferroelectric layer has been etched but also when another layers such as inter-layer insulators and interconnections are then etched later. In this case, the mechanism of the etching damage is different between when the ferroelectric layer has been etched and when another layers such as inter-layer insulators and interconnections are then etched later. The above ferroelectric layer is made of SBT, whilst the inter-layer insulators are made of silicon dioxide and the interconnection layers may be made of aluminum. In order to etch the materials other than SBT film, reducing gases such as CHF.sub.3 or BCl.sub.3 are used whereby a reducing reaction is caused, resulting in an oxygen deficiency.
Even if no such reducing gas is used but a high etching rate gas such as Cl2 possessing a high etching rate to the resist is used, then the resist film used for selective etching is decomposed by a reaction of Cl with O. Such reaction of Cl with 0 generates H which might provide the influences to the SBT ferroelectric film.
After the aluminum interconnection layer has been etched, then a high temperature heat treatment could never be carried out in order to avoid oxidation of aluminum or avoid malting of aluminum. Particularly, etching to aluminum is problem. In this case, the reducing function is smaller than the above case. Notwithstanding, not only the leakage of current is increased but also deteriorations of the reliability and durability by aging of the capacitor as well as deteriorations of endurance to the operations of writing data into the memory are also problem.
In the above circumstances, it bad been required to develop a novel method of forming a semiconductor memory device free from the above problems and disadvantages as described above.